On 10 March 2017 at 15:21, Ludovic Desroches
<ludovic.desroches@xxxxxxxxx> wrote:
> From: Ludovic Desroches <ludovic.desroches@xxxxxxxxxxxxx>
>
> The commit e173f8911f09 mmc: core: Update CMD13 polling policy when
> switch to HS DDR mode in addition to fix the management of CRC error,
> changes the place where the DDR52 timing is set.
>
> Before this commit, the sequence was:
> - set width to 8 with MMC_HS timing
> - send the switch command
> - check the status
> - set width to 8 with MMC_DDR52 timing
> - send the switch command
> - check the status
> Now:
> - set width to 8 with MMC_HS timing
> - send the switch command
> - set width to 8 with MMC_DDR52 timing
> - check the status
>
> It may lead to get an error when checking the status with some devices.
>
> Signed-off-by: Ludovic Desroches <ludovic.desroches@xxxxxxxxxxxxx>
> ---
> drivers/mmc/core/mmc.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
> index 0fccca0..b837148 100644
> --- a/drivers/mmc/core/mmc.c
> +++ b/drivers/mmc/core/mmc.c
> @@ -1062,7 +1062,7 @@ static int mmc_select_hs_ddr(struct mmc_card *card)
> EXT_CSD_BUS_WIDTH,
> ext_csd_bits,
> card->ext_csd.generic_cmd6_time,
> - MMC_TIMING_MMC_DDR52,
> + 0,
> true, true, true);
> if (err) {
> pr_err("%s: switch to bus width %d ddr failed\n",
> @@ -1106,6 +1106,9 @@ static int mmc_select_hs_ddr(struct mmc_card *card)
> if (err)
> err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_330);
>
> + if (!err)
> + mmc_set_timing(host, MMC_TIMING_MMC_DDR52);
> +
> return err;
> }
>
> --
> 2.9.0
>
We had other reports for similar problems. The following change fix
those issues, have you tried this out?
[PATCH] mmc: core: Restore parts of the polling policy when switch to HS/HS DDR
https://patchwork.kernel.org/patch/9515239/
Kind regards
Uffe
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