On 21 May 2015 at 13:45, Joakim Tjernlund <joakim.tjernlund@xxxxxxxxxxxx> wrote: > On Thu, 2015-05-21 at 18:56 +0800, Kevin Hao wrote: >> On Thu, May 21, 2015 at 09:24:43AM +0000, Joakim Tjernlund wrote: >> > The HW 8BIT can be confused with SDHCI_CTRL_HISPD(0x04) as it is the same bit. >> > >> > However, now I see that esdhc_writeb() has >> > /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */ >> > if (reg == SDHCI_HOST_CONTROL) >> > val &= ~ESDHC_HOST_CONTROL_RES; >> > and >> > #define ESDHC_HOST_CONTROL_RES 0x05 >> > >> > so any esdhc_writeb() to SDHCI_HOST_CONTROL will clear the HW 8BIT. >> > What a mess. >> >> Aha, I see. Thanks for the explanation. > > There is also the common patten of > val = esdhc_readb(..) > val |= some bit > esdhc_writeb(val) > This will also stomp on 8BIT > > I cannot find a Maintainer, is there one? Nope. > This driver really needs a Freescale maintainer who can navigate > the subtile differences between Freescale SOCs I certainly would welcome that! Kind regards Uffe -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
