On Sun, May 20, 2012 at 5:27 AM, Seungwon Jeon <tgih.jun@xxxxxxxxxxx> wrote:
> In case of "host->bus_hz < slot->clock", divider value is
> miscalculated. And clock divider register value is multiple
> of 2. If calculated divider value is odd number, result can
> be over-clocking.
>
> Signed-off-by: Seungwon Jeon <tgih.jun@xxxxxxxxxxx>
> ---
> drivers/mmc/host/dw_mmc.c | 10 ++++++----
> 1 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index f2f8463..c87745e 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -617,14 +617,16 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot)
> u32 div;
>
> if (slot->clock != host->current_speed) {
> - if (host->bus_hz % slot->clock)
> + div = host->bus_hz / slot->clock;
> + if (host->bus_hz % slot->clock &&
> + host->bus_hz > slot->clock)
> /*
> * move the + 1 after the divide to prevent
> * over-clocking the card.
> */
This comment seems to be no longer relevant so it should be removed.
> - div = ((host->bus_hz / slot->clock) >> 1) + 1;
> - else
> - div = (host->bus_hz / slot->clock) >> 1;
> + div += 1;
> +
> + div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0;
>
> dev_info(&slot->mmc->class_dev,
> "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
> --
> 1.7.0.4
>
>
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