On Tue, 7 Dec 2010, Philip Rakity wrote:
>
> This code extends software clock gating in the MMC layer by adding the ability
> to indicate that the SD controller supports hardware clock gating.
>
> Hardware clock gating is enabled by setting the MMC capability
> MMC_CAP_HW_CLOCK_GATING in the SD driver.
>
> eg: host->mmc->caps |= MMC_CAP_HW_CLOCK_GATING
>
> The approach follows the suggestion of Nico Pitre.
>
> SD/MMC/eMMC cards use dynamic clocks
> SDIO uses continuous clocks to properly detect SDIO card interrupts
>
> The code has been tested using marvell linux for MMP2. The Marvell
> controller support H/W clock gating.
>
> Signed-off-by: Philip Rakity <prakity@xxxxxxxxxxx>
> Signed-off-by: Mark F. Brown <markb@xxxxxxxxxxx>
There is one needless change in your patch:
> @@ -178,10 +181,13 @@ void mmc_host_clk_gate(struct mmc_host *host)
> {
> unsigned long flags;
>
> + if (host->caps & MMC_CAP_HW_CLOCK_GATING)
> + return;
> +
> spin_lock_irqsave(&host->clk_lock, flags);
> host->clk_requests--;
> if (mmc_host_may_gate_card(host->card) &&
> - !host->clk_requests)
> + !host->clk_requests)
The second line of the if() was properly aligned before.
Other than that...
Acked-by: Nicolas Pitre <nicolas.pitre@xxxxxxxxxx>
Nicolas
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