On Wed, Sep 15, 2010 at 6:10 PM, Wolfram Sang <w.sang@xxxxxxxxxxxxxx> wrote: > On Wed, Sep 15, 2010 at 11:35:18AM +0800, zhangfei gao wrote: > >> > Is the 8-bit support really according to the standard? I wonder because >> > the bit currently used by sdhci.c is marked as "reserved/new assignment >> > now allowed" in the simplified v2.0 spec. >> >> Attached capacity in sdh 3.0. >> 6-bit base clock frequece is support in 1.0 and 2.0, support 10M to 63M. >> 8-bit is supported in 3.0, and support 10M to 255M. > > I meant 8-bit bus width. Which bit in which register selects this? The 8-bit bus width usually used in embeded mmc, like Micron emmc and sandisk emmc, bit[5] of host controller (0x28h) is added in sdh spec 3.0, and the patch is already in the latest kernel. > > -- > Pengutronix e.K. | Wolfram Sang | > Industrial Linux Solutions | http://www.pengutronix.de/ | > > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.10 (GNU/Linux) > > iEYEARECAAYFAkyQm4sACgkQD27XaX1/VRuafACgxxhhat+eHjTEFspi+Nwn3/K8 > gVsAnRuhxy2C452n57jxhDDYdNdtZrP6 > =H7hA > -----END PGP SIGNATURE----- > > -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
