Re: [patch v2 1/1]sdhci support 10 bit divided clock Mode for spec 3.0

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On Mon, Aug 16, 2010 at 07:54:14PM +0100, David Vrabel wrote:
> Matt Fleming wrote:
> > 
> > Sorry, I did mean to reply to this sooner but I've been travelling. Yeah
> > David, you're right. Zhangfei, have you confused the Programmable Clock
> > Mode in the 3.00 spec here with 10-bit Divided Clock Mode?
> > 
> > Both 8-bit Divided Clock Mode and 10-bit Divided Clock Mode require the
> > divisor to be a power of two.
> 
> The power-of-two requirement only applies to 2.00 controller.  From
> section 2.2.14 of the spec.
> 
>    "(2) 10-bit Divided Clock Mode
>    Host Controller Version 3.00 supports this mandatory mode instead of
>    the 8-bit Divided Clock Mode. The length of divider is extended to
>    10bits and all divider values shall be supported."
> 
> 3.00 dividers can be any multiple of two.

Yep, you're right. I misread the spec. My bad.
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