Re: [patch v2 1/1]sdhci support 10 bit divided clock Mode for spec 3.0

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On Mon, Aug 16, 2010 at 05:07:15PM +0100, David Vrabel wrote:
> zhangfei gao wrote:
> > 
> > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> > index 913555e..32dcac9 100644
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> [...]
> > @@ -1001,13 +1001,23 @@ static void sdhci_set_clock(struct sdhci_host
> > *host, unsigned int clock)
> >  	if (clock == 0)
> >  		goto out;
> > 
> > -	for (div = 1;div < 256;div *= 2) {
> > -		if ((host->max_clk / div) <= clock)
> > -			break;
> > +	if (host->version >= SDHCI_SPEC_300)
> > +		max_div = 2046;
> > +	else
> > +		max_div = 256;
> > +
> > +	if(host->max_clk <= clock)
> > +		div = 1;
> > +	else {
> > +		for (div = 2; div < max_div; div += 2) {
> > +			if ((host->max_clk / div) <= clock)
> > +				break;
> > +		}
> 
> This isn't correct.  The divisor must be a power of two for 2.00
> controllers.

Sorry, I did mean to reply to this sooner but I've been travelling. Yeah
David, you're right. Zhangfei, have you confused the Programmable Clock
Mode in the 3.00 spec here with 10-bit Divided Clock Mode?

Both 8-bit Divided Clock Mode and 10-bit Divided Clock Mode require the
divisor to be a power of two. Support for Programmable Clock Mode would
require a bit more work because not all clock multiplier values are
valid. Support for that should be done as a separate patch.
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