>From: linux-omap-owner@xxxxxxxxxxxxxxx [mailto:linux-omap- >owner@xxxxxxxxxxxxxxx] On Behalf Of David Vrabel >Sent: Wednesday, February 17, 2010 7:10 PM > >David Vrabel wrote: >> >> +static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) >> +{ >> + struct omap_hsmmc_host *host = mmc_priv(mmc); >> + u32 ie, con; >> + unsigned long flags; >> + >> + spin_lock_irqsave(&host->irq_lock, flags); >> + >> + /* >> + * When interrupts are enabled, CTPL must be set to enable >> + * DAT1 input buffer (or the card interrupt is always >> + * asserted) and FCLK must be enabled else wakeup does not >> + * work. >> + * >> + * FIXME: the power save code probably shouldn't be playing >> + * with FCLK and allow the clock subsystem to put it into >> + * smart-idle mode instead. >> + */ >> + con = OMAP_HSMMC_READ(host->base, CON); >> + ie = OMAP_HSMMC_READ(host->base, IE); >> + if (enable) { >> + clk_enable(host->fclk); >> + ie |= CIRQ_ENABLE; >> + con |= CTPL; >> + } else { >> + clk_disable(host->fclk); >> + ie &= ~CIRQ_ENABLE; >> + con &= ~CTPL; >> + } >> + OMAP_HSMMC_WRITE(host->base, CON, con); >> + OMAP_HSMMC_WRITE(host->base, IE, ie); >> + >> + spin_unlock_irqrestore(&host->irq_lock, flags); >> +} > >This isn't doing a posted write flush but when it's added this ends up >looking like: > > spin_lock_irqsave(&host->lock, flags); > > /* > * When interrupts are enabled, CTPL must be set to enable > * DAT1 input buffer (or the card interrupt is always > * asserted) and FCLK must be enabled else wakeup does not > * work. Take care to disable FCLK after all the register > * accesses as they might not complete if FCLK is off. > * > * FIXME: the power save code probably shouldn't be playing > * with FCLK and allow the clock subsystem to put it into > * smart-idle mode instead. > */ > con = OMAP_HSMMC_READ(host->base, CON); > ie = OMAP_HSMMC_READ(host->base, IE); > if (enable) { > clk_enable(host->fclk); > ie |= CIRQ_ENABLE; > con |= CTPL; > } else { > ie &= ~CIRQ_ENABLE; > con &= ~CTPL; > } > OMAP_HSMMC_WRITE(host->base, CON, con); > OMAP_HSMMC_WRITE(host->base, IE, ie); > OMAP_HSMMC_READ(host->base, IE); /* flush posted write */ > if (!enable) { > clk_disable(host->fclk); > } > > spin_unlock_irqrestore(&host->lock, flags); > >Could someone from TI could comment on why disabling FCLK affects >register read? Most IPs will require both iclk and fclk to be active in order to access them. Some simple IP can work with only an iclk. Otherwise, accessing a register while enabling only iclk will lead to unpredictable behavior. Regards, Benoit Texas Instruments France SA, 821 Avenue Jack Kilby, 06270 Villeneuve Loubet. 036 420 040 R.C.S Antibes. Capital de EUR 753.920 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
