David Vrabel wrote:
>
> +static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
> +{
> + struct omap_hsmmc_host *host = mmc_priv(mmc);
> + u32 ie, con;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&host->irq_lock, flags);
> +
> + /*
> + * When interrupts are enabled, CTPL must be set to enable
> + * DAT1 input buffer (or the card interrupt is always
> + * asserted) and FCLK must be enabled else wakeup does not
> + * work.
> + *
> + * FIXME: the power save code probably shouldn't be playing
> + * with FCLK and allow the clock subsystem to put it into
> + * smart-idle mode instead.
> + */
> + con = OMAP_HSMMC_READ(host->base, CON);
> + ie = OMAP_HSMMC_READ(host->base, IE);
> + if (enable) {
> + clk_enable(host->fclk);
> + ie |= CIRQ_ENABLE;
> + con |= CTPL;
> + } else {
> + clk_disable(host->fclk);
> + ie &= ~CIRQ_ENABLE;
> + con &= ~CTPL;
> + }
> + OMAP_HSMMC_WRITE(host->base, CON, con);
> + OMAP_HSMMC_WRITE(host->base, IE, ie);
> +
> + spin_unlock_irqrestore(&host->irq_lock, flags);
> +}
This isn't doing a posted write flush but when it's added this ends up
looking like:
spin_lock_irqsave(&host->lock, flags);
/*
* When interrupts are enabled, CTPL must be set to enable
* DAT1 input buffer (or the card interrupt is always
* asserted) and FCLK must be enabled else wakeup does not
* work. Take care to disable FCLK after all the register
* accesses as they might not complete if FCLK is off.
*
* FIXME: the power save code probably shouldn't be playing
* with FCLK and allow the clock subsystem to put it into
* smart-idle mode instead.
*/
con = OMAP_HSMMC_READ(host->base, CON);
ie = OMAP_HSMMC_READ(host->base, IE);
if (enable) {
clk_enable(host->fclk);
ie |= CIRQ_ENABLE;
con |= CTPL;
} else {
ie &= ~CIRQ_ENABLE;
con &= ~CTPL;
}
OMAP_HSMMC_WRITE(host->base, CON, con);
OMAP_HSMMC_WRITE(host->base, IE, ie);
OMAP_HSMMC_READ(host->base, IE); /* flush posted write */
if (!enable) {
clk_disable(host->fclk);
}
spin_unlock_irqrestore(&host->lock, flags);
Could someone from TI could comment on why disabling FCLK affects
register read?
David
--
David Vrabel, Senior Software Engineer, Drivers
CSR, Churchill House, Cambridge Business Park, Tel: +44 (0)1223 692562
Cowley Road, Cambridge, CB4 0WZ http://www.csr.com/
Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
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