On 04/24/2014 10:53 AM, Rik van Riel wrote: >> I do agree that it's ambiguous at best. I'll go see if anybody cares to >> update that bit. > > I suspect that IF the TLB actually uses a 2MB entry for the > translation, a single INVLPG will work. > > However, the CPU is free to cache the translations for a 2MB > region with a bunch of 4kB entries, if it wanted to, so in > the end we have no guarantee that an INVLPG will actually do > the right thing... > > The same is definitely true for 1GB vs 2MB entries, with > some CPUs being capable of parsing page tables with 1GB > entries, but having no TLB entries for 1GB translations. I believe we _do_ have such a guarantee. There's another bit in the SDM that someone pointed out to me in a footnote in "4.10.4.1": 1. If the paging structures map the linear address using a page larger than 4 KBytes and there are multiple TLB entries for that page (see Section 4.10.2.3), the instruction invalidates all of them. While that's not in the easiest-to-find place in the documents, it looks pretty clear. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@xxxxxxxxx. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@xxxxxxxxx";> email@xxxxxxxxx </a>