On Mon, Nov 25, 2013 at 03:55:43PM -0800, H. Peter Anvin wrote: > On 11/25/2013 10:02 AM, Paul E. McKenney wrote: > > > > I still do not believe that it does. Again, strangely enough. > > > > We need to ask someone in Intel that understands this all the way down > > to the silicon. The guy I used to rely on for this no longer works > > at Intel. > > > > Do you know someone who fits this description, or should I start sending > > cold-call emails to various Intel contacts? > > Feel free to poke me if you need any help. My biggest question is the definition of "Memory ordering obeys causality (memory ordering respects transitive visibility)" in Section 3.2.2 of the "Intel® 64 and IA-32 Architectures Developer's Manual: Vol. 3A" dated March 2013 from: http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.html I am guessing that is orders loads as well as stores, so that a load is said to be "visible" to some other CPU once that CPU no longer has the opportunity to affect the return value from the load. Is that a reasonable interpretation? More generally, is the model put forward by Sewell et al. in "x86-TSO: A Rigorous and Usable Programmer's Model for x86 Multiprocessors" accurate? This is on pages 4 and 5 here: http://www.cl.cam.ac.uk/~pes20/weakmemory/cacm.pdf Thanx, Paul -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@xxxxxxxxx. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@xxxxxxxxx";> email@xxxxxxxxx </a>