Wei Xu <weixugc@xxxxxxxxxx> writes: > On Tue, May 10, 2022 at 4:38 AM Aneesh Kumar K.V > <aneesh.kumar@xxxxxxxxxxxxx> wrote: >> >> Alistair Popple <apopple@xxxxxxxxxx> writes: >> >> > Wei Xu <weixugc@xxxxxxxxxx> writes: >> > >> >> On Thu, May 5, 2022 at 5:19 PM Alistair Popple <apopple@xxxxxxxxxx> wrote: >> >>> >> >>> Wei Xu <weixugc@xxxxxxxxxx> writes: >> >>> >> >>> [...] >> >>> >> >>> >> > >> >>> >> > >> >>> >> > Tiering Hierarchy Initialization >> >>> >> > `==============================' >> >>> >> > >> >>> >> > By default, all memory nodes are in the top tier (N_TOPTIER_MEMORY). >> >>> >> > >> >>> >> > A device driver can remove its memory nodes from the top tier, e.g. >> >>> >> > a dax driver can remove PMEM nodes from the top tier. >> >>> >> >> >>> >> With the topology built by firmware we should not need this. >> >>> >> >>> I agree that in an ideal world the hierarchy should be built by firmware based >> >>> on something like the HMAT. But I also think being able to override this will be >> >>> useful in getting there. Therefore a way of overriding the generated hierarchy >> >>> would be good, either via sysfs or kernel boot parameter if we don't want to >> >>> commit to a particular user interface now. >> >>> >> >>> However I'm less sure letting device-drivers override this is a good idea. How >> >>> for example would a GPU driver make sure it's node is in the top tier? By moving >> >>> every node that the driver does not know about out of N_TOPTIER_MEMORY? That >> >>> could get messy if say there were two drivers both of which wanted their node to >> >>> be in the top tier. >> >> >> >> The suggestion is to allow a device driver to opt out its memory >> >> devices from the top-tier, not the other way around. >> > >> > So how would demotion work in the case of accelerators then? In that >> > case we would want GPU memory to demote to DRAM, but that won't happen >> > if both DRAM and GPU memory are in N_TOPTIER_MEMORY and it seems the >> > only override available with this proposal would move GPU memory into a >> > lower tier, which is the opposite of what's needed there. >> >> How about we do 3 tiers now. dax kmem devices can be registered to >> tier 3. By default all numa nodes can be registered at tier 2 and HBM or >> GPU can be enabled to register at tier 1. ? > > This makes sense. I will send an updated RFC based on the discussions so far. Thanks! The sense I got from LSF/MM was that we should initially try keep things simple by limiting it to two tiers. However I don't think there was strong opposition to adding a third tier to support GPU+CPU+PMEM, and it does seem like it might even be simpler to just have three tiers and assign devices as suggested. >> -aneesh
