On Wed, 2 Mar 2022 16:46:23 +0800, Muchun Song wrote:
> When a contiguous HugeTLB page is mapped, set_pte_at() will be called
> CONT_PTES/CONT_PMDS times. Therefore, __sync_icache_dcache() will
> flush cache multiple times if the page is executable (to ensure
> the I-D cache coherency). However, the first flushing cache already
> covers subsequent cache flush operations. So only flusing cache
> for the head page if it is a HugeTLB page to avoid redundant cache
> flushing. In the next patch, it is also depends on this change
> since the tail vmemmap pages of HugeTLB is mapped with read-only
> meanning only head page struct can be modified.
>
> [...]
Applied first patch only to arm64 (for-next/mm), thanks!
[1/2] arm64: avoid flushing icache multiple times on contiguous HugeTLB
https://git.kernel.org/arm64/c/cf5a501d985b
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
