On 2/5/2021 10:41 AM, Yu, Yu-cheng wrote:
On 2/4/2021 12:27 PM, Dave Hansen wrote:
On 2/4/21 12:19 PM, Kees Cook wrote:
(e) A page where the processor observed a Write=1 PTE, started a
write, set
Dirty=1, but then observed a Write=0 PTE. That's possible
today, but
will not happen on processors that support shadow stack.
What happens for "e" with/without CET? It sounds like direct writes to
such pages will be (correctly) rejected by the MMU?
A page fault would be generated regardless of CET support.
If CET were not around, the fault would be reported as a present, write
fault.
If this happened and CET were around (which shouldn't happen in
practice, it means we have a hardware issue) a page fault exception is
generated.
Thanks for the clarification. With or without CET, direct write to
Write=0, Dirty=1 PTE triggers page fault.
Yu-cheng, I'm not sure there's enough debugging around to
tell us if this happens. Would we even notice?
That potential hardware issue is, on a CET-capable system, a processor
writes to a Write=1, Dirty=0 page, and then observes the PTE is Write=0,
Dirty=1. Let me think about it...
One way to detect the potential issue is adding a check when a
non-shadow stack page's PTE goes from RW=0 to RW=1, like the following...
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 29aa6f07e3c9..241b94a0fa77 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -405,6 +405,8 @@ static inline pte_t pte_mkyoung(pte_t pte)
static inline pte_t pte_mkwrite(pte_t pte)
{
if (cpu_feature_enabled(X86_FEATURE_SHSTK)) {
+ WARN_ONCE((pte_flags(pte) & (_PAGE_RW | _PAGE_DIRTY)) ==
+ _PAGE_DIRTY, "Found transient shadow stack PTE\n");
if (pte_flags(pte) & _PAGE_COW) {
pte = pte_clear_flags(pte, _PAGE_COW);
pte = pte_set_flags(pte, _PAGE_DIRTY);
I run all my routine stress tests with the changes, and do not see any
warning triggered. If this change is desirable, we can probably add
#ifdef CONFIG_DEBUG_VM around it and make it a separate patch.
--
Yu-cheng
