Re: [PATCH v18 05/25] x86/fpu/xstate: Introduce CET MSR and XSAVES supervisor states

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On 1/29/2021 2:53 PM, Dave Hansen wrote:
On 1/29/21 2:35 PM, Yu, Yu-cheng wrote:
Andy Cooper just mentioned on IRC about this nugget in the spec:

     XRSTORS on CET state will do reserved bit and canonicality
     checks on the state in similar manner as done by the WRMSR to
     these state elements.

We're using copy_kernel_to_xregs_err(), so the #GP *should* be OK.
Could we prove this out in practice, please?

Do we want to verify that setting reserved bits in CET XSAVES states
triggers GP?  Then, yes, I just verified it again.  Thanks for
reminding.  Do we have any particular case relating to this?

I want to confirm that it triggers #GP and kills userspace without the
kernel WARN'ing or otherwise being visibly unhappy.

For sigreturn, shadow stack pointer is checked against its restore token and must be smaller than TASK_SIZE_MAX. Sigreturn cannot set any MSR_IA32_U_CET reserved bits.


What about the return-to-userspace path after a ptracer writes content
to the CET fields?   I don't see the same tolerance for errors in
__fpregs_load_activate(), for instance.


Good thought. I have not sent out my revised PTRACE patch, but values from user will be checked for valid address and reserved bits.

--
Yu-cheng





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