Re: [PATCH 16/17] riscv: clear the instruction cache and all registers when booting

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To: Atish Patra <Atish.Patra@xxxxxxx>
Subject: Re: [PATCH 16/17] riscv: clear the instruction cache and all registers when booting
From: "hch@xxxxxx" <hch@xxxxxx>
Date: Tue, 13 Aug 2019 17:37:07 +0200
Cc: "hch@xxxxxx" <hch@xxxxxx>, "paul.walmsley@xxxxxxxxxx" <paul.walmsley@xxxxxxxxxx>, "palmer@xxxxxxxxxx" <palmer@xxxxxxxxxx>, "linux-mm@xxxxxxxxx" <linux-mm@xxxxxxxxx>, Damien Le Moal <Damien.LeMoal@xxxxxxx>, "linux-riscv@xxxxxxxxxxxxxxxxxxx" <linux-riscv@xxxxxxxxxxxxxxxxxxx>, "linux-kernel@xxxxxxxxxxxxxxx" <linux-kernel@xxxxxxxxxxxxxxx>
In-reply-to: <78919862d11f6d56446f8fffd8a1a8c601ea5c32.camel@wdc.com>
References: <20190624054311.30256-1-hch@lst.de> <20190624054311.30256-17-hch@lst.de> <78919862d11f6d56446f8fffd8a1a8c601ea5c32.camel@wdc.com>
User-agent: Mutt/1.5.17 (2007-11-01)

On Mon, Jul 01, 2019 at 09:26:18PM +0000, Atish Patra wrote:
> That means it should be done for S-mode as well. Right ?

For S-mode the bootloader/sbi should take care of it.

References:
- RISC-V nommu support v2
  - From: Christoph Hellwig
- [PATCH 16/17] riscv: clear the instruction cache and all registers when booting
  - From: Christoph Hellwig
- Re: [PATCH 16/17] riscv: clear the instruction cache and all registers when booting
  - From: Atish Patra

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