On 31/07/2019 10:27, Sven Schnelle wrote: > Hi Steven, > > On Mon, Jul 29, 2019 at 12:32:25PM +0100, Steven Price wrote: >> >> parisc is more interesting and I'm not sure if this is necessarily >> correct. I originally proposed a patch with the line "For parisc, we >> don't support large pages, so add stubs returning 0" which got Acked by >> Helge Deller. However going back to look at that again I see there was a >> follow up thread[2] which possibly suggests I was wrong? > > I just started a week ago implementing ptdump for PA-RISC. Didn't notice that > you're working on making it generic, which is nice. I'll adjust my code > to use the infrastructure you're currently developing. Great, hopefully it will make it easier to implement. >> Can anyone shed some light on whether parisc does support leaf entries >> of the page table tree at a higher than the normal depth? >> >> [1] https://lkml.org/lkml/2019/2/27/572 >> [2] https://lkml.org/lkml/2019/3/5/610 > > My understanding is that PA-RISC only has leaf entries on PTE level. Yes, that's my current interpretation. >> The intention is that the page table walker would be available for all >> architectures so that it can be used in any generic code - PTDUMP simply >> seemed like a good place to start. >> >>> Now that pmd_leaf() and pud_leaf() are getting used in walk_page_range() these >>> functions need to be defined on all arch irrespective if they use PTDUMP or not >>> or otherwise just define it for archs which need them now for sure i.e x86 and >>> arm64 (which are moving to new generic PTDUMP framework). Other archs can >>> implement these later. > > I'll take care of the PA-RISC part - for 32 bit your generic code works, for 64Bit > i need to learn a bit more about the following hack: > > arch/parisc/include/asm/pgalloc.h:15 > /* Allocate the top level pgd (page directory) > * > * Here (for 64 bit kernels) we implement a Hybrid L2/L3 scheme: we > * allocate the first pmd adjacent to the pgd. This means that we can > * subtract a constant offset to get to it. The pmd and pgd sizes are > * arranged so that a single pmd covers 4GB (giving a full 64-bit > * process access to 8TB) so our lookups are effectively L2 for the > * first 4GB of the kernel (i.e. for all ILP32 processes and all the > * kernel for machines with under 4GB of memory) > */ As far as I understand this, the page table tree isn't any different here. It's just that there's a PMD which is allocated at the same time as the PGD. The PGD's first entry then points to the PMD (P4D/PUD are folded). There are then some tricks which means that for addresses < 4GB the PGD stage can be skipped because you already know where the relevant PMD is. However, nothing should stop a simple walk from PGD down - it's just an optimisation to remove the pointer fetch from PGD in the usual case for accesses < 4GB. > I see that your change clear P?D entries when p?d_bad() returns true, which - i think - > would be the case with the PA-RISC implementation. The only case where p?d_bad() is checked is at the PGD and P4D levels (unless I'm missing something?). I have to admit I'm a little unsure about this. Basically the code as it stands doesn't allow leaf entries at PGD or P4D. I'm not aware of any architectures that do this though. Thanks, Steve
