On 03/10/2011 01:05 PM, Chris Metcalf wrote:
Tile has incoherent icaches, so they must be explicitly invalidated when necessary. Until now we have done so at tlb flush and context switch time, which means more invalidation than strictly necessary. The new model for icache flush is: - When we fault in a page as executable, we set an "Exec" bit in the "struct page" information; the bit stays set until page free time. (We use the arch_1 page bit for our "Exec" bit.) - At page free time, if the Exec bit is set, we do an icache flush. This should happen relatively rarely: e.g., deleting a binary from disk, or evicting a binary's pages from the page cache due to memory pressure. Signed-off-by: Chris Metcalf<cmetcalf@xxxxxxxxxx>
Nice trick. Acked-by: Rik van Riel <riel@xxxxxxxxxx> -- All rights reversed -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@xxxxxxxxxx For more info on Linux MM, see: http://www.linux-mm.org/ . Fight unfair telecom internet charges in Canada: sign http://stopthemeter.ca/ Don't email: <a href=mailto:"dont@xxxxxxxxx";> email@xxxxxxxxx </a>