On Thu, 2018-06-07 at 11:30 -0700, Andy Lutomirski wrote:
> On Thu, Jun 7, 2018 at 7:41 AM Yu-cheng Yu <yu-cheng.yu@xxxxxxxxx> wrote:
> >
> > Set and restore shadow stack pointer for signals.
>
> How does this interact with siglongjmp()?
>
> This patch makes me extremely nervous due to the possibility of ABI
> issues and CRIU breakage.
Longjmp/Siglongjmp is handled in GLIBC and basically the shadow stack
pointer is unwound. There could be some unexpected conditions.
However, we run all GLIBC tests.
>
> > diff --git a/arch/x86/include/uapi/asm/sigcontext.h b/arch/x86/include/uapi/asm/sigcontext.h
> > index 844d60eb1882..6c8997a0156a 100644
> > --- a/arch/x86/include/uapi/asm/sigcontext.h
> > +++ b/arch/x86/include/uapi/asm/sigcontext.h
> > @@ -230,6 +230,7 @@ struct sigcontext_32 {
> > __u32 fpstate; /* Zero when no FPU/extended context */
> > __u32 oldmask;
> > __u32 cr2;
> > + __u32 ssp;
> > };
> >
> > /*
> > @@ -262,6 +263,7 @@ struct sigcontext_64 {
> > __u64 trapno;
> > __u64 oldmask;
> > __u64 cr2;
> > + __u64 ssp;
> >
> > /*
> > * fpstate is really (struct _fpstate *) or (struct _xstate *)
> > @@ -320,6 +322,7 @@ struct sigcontext {
> > struct _fpstate __user *fpstate;
> > __u32 oldmask;
> > __u32 cr2;
> > + __u32 ssp;
>
> Is it actually okay to modify these structures like this? They're
> part of the user ABI, and I don't know whether any user code relies on
> the size being constant.
>
> > +int cet_push_shstk(int ia32, unsigned long ssp, unsigned long val)
> > +{
> > + if (val >= TASK_SIZE)
> > + return -EINVAL;
>
> TASK_SIZE_MAX. But I'm a bit unsure why you need this check at all.
If an invalid address is put on the shadow stack, the task will get a
control protection fault. I will change it to TASK_SIZE_MAX.
>
> > +int cet_restore_signal(unsigned long ssp)
> > +{
> > + if (!current->thread.cet.shstk_enabled)
> > + return 0;
> > + return cet_set_shstk_ptr(ssp);
> > +}
>
> This will blow up if the shadow stack enabled state changes in a
> signal handler. Maybe we don't care.
Yes, the task will get a control protection fault.
