On 2010-12-23 15:20, Russell King - ARM Linux wrote: > On Thu, Dec 23, 2010 at 03:08:21PM +0100, Tomasz Fujak wrote: >> On 2010-12-23 14:51, Russell King - ARM Linux wrote: >>> On Thu, Dec 23, 2010 at 02:41:26PM +0100, Michal Nazarewicz wrote: >>>> Russell King - ARM Linux <linux@xxxxxxxxxxxxxxxx> writes: >>>>> Has anyone addressed my issue with it that this is wide-open for >>>>> abuse by allocating large chunks of memory, and then remapping >>>>> them in some way with different attributes, thereby violating the >>>>> ARM architecture specification? >>>>> >>>>> In other words, do we _actually_ have a use for this which doesn't >>>>> involve doing something like allocating 32MB of memory from it, >>>>> remapping it so that it's DMA coherent, and then performing DMA >>>>> on the resulting buffer? >>>> Huge pages. >>>> >>>> Also, don't treat it as coherent memory and just flush/clear/invalidate >>>> cache before and after each DMA transaction. I never understood what's >>>> wrong with that approach. >>> If you've ever used an ARM system with a VIVT cache, you'll know what's >>> wrong with this approach. >>> >>> ARM systems with VIVT caches have extremely poor task switching >>> performance because they flush the entire data cache at every task switch >>> - to the extent that it makes system performance drop dramatically when >>> they become loaded. >>> >>> Doing that for every DMA operation will kill the advantage we've gained >>> from having VIPT caches and ASIDs stone dead. >> This statement effectively means: don't map dma-able memory to the CPU >> unless it's uncached. Have I missed anything? > I'll give you another solution to the problem - lobby ARM Ltd to have > this restriction lifted from the architecture specification, which > will probably result in the speculative prefetching also having to be > removed. > Isn't disabling Speculative Accesses forwarding to the AXI bus the solution to our woes? At least on the A8, which happens to be paired with non-IOMMU capable IPs on our SoCs. On A9 the bit is gone (or has it moved?), but we have IOMMU here so the CMA isn't needed. http://infocenter.arm.com/ Cortex-A8 Technical Reference Manual Revision: r3p2 3.2.26. c1, Auxiliary Control Register CP15, c1, c0, bit 4: Enables speculative accesses on AXI > That would be my preferred solution if I had the power to do so, but > I have to live with what ARM Ltd (and their partners such as yourselves) > decide should end up in the architecture specification. > -- > To unsubscribe from this list: send the line "unsubscribe linux-media" in > the body of a message to majordomo@xxxxxxxxxxxxxxx > More majordomo info at http://vger.kernel.org/majordomo-info.html > -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@xxxxxxxxxx For more info on Linux MM, see: http://www.linux-mm.org/ . Fight unfair telecom policy in Canada: sign http://dissolvethecrtc.ca/ Don't email: <a href=mailto:"dont@xxxxxxxxx";> email@xxxxxxxxx </a>