On Tue, Aug 02, 2016 at 03:27:06PM -0700, Nadav Amit wrote:
> Rafael Aquini <aquini@xxxxxxxxxx> wrote:
>
> > While backporting 71b3c126e611 ("x86/mm: Add barriers and document switch_mm()-vs-flush synchronization")
> > we stumbled across a possibly missing barrier at flush_tlb_page().
>
> I too noticed it and submitted a similar patch that never got a response [1].
>
As far as I understood Andy's rationale for the original patch you need
a full memory barrier there in flush_tlb_page to get that cache-eviction
race sorted out.
Regards,
-- Rafael
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