On 19/10/2024 09:10, Aleksandar Rikalo wrote:
From: Paul Burton <paulburton@xxxxxxxxxx> In a multi-cluster MIPS system, there are multiple GICs - one in each cluster - each of which has its independent counter. The counters in each GIC are not synchronized in any way, so they can drift relative to one another through the lifetime of the system. This is problematic for a clock source which ought to be global. Avoid problems by always accessing cluster 0's counter, using cross-cluster register access. This adds overhead so it is applied only on multi-cluster systems. Signed-off-by: Paul Burton <paulburton@xxxxxxxxxx> Signed-off-by: Chao-ying Fu <cfu@xxxxxxxxxxxx> Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@xxxxxxxxxx> Signed-off-by: Aleksandar Rikalo <arikalo@xxxxxxxxx> Tested-by: Serge Semin <fancer.lancer@xxxxxxxxx> ---
May I take this patch through the clocksource tree ? -- <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
