On Mon, Jul 22, 2024 at 03:15:39PM +0200, Gregory CLEMENT wrote:
> When the CM block migrated from CM2.5 to CM3.0, the address offset for
> the Global CSR Access Privilege register was modified. We saw this in
> the "MIPS64 I6500 Multiprocessing System Programmer's Guide," it is
> stated that "the Global CSR Access Privilege register is located at
> offset 0x0120" in section 5.4. It is at least the same for I6400.
>
> This fix allows to use the VP cores in SMP mode if the reset values
> were modified by the bootloader.
>
> Based on the work of Vladimir Kondratiev
> <vladimir.kondratiev@xxxxxxxxxxxx> and the feedback from Jiaxun Yang
> <jiaxun.yang@xxxxxxxxxxx>.
>
> Fixes: 197e89e0984a ("MIPS: mips-cm: Implement mips_cm_revision")
> Signed-off-by: Gregory CLEMENT <gregory.clement@xxxxxxxxxxx>
> ---
> Changes in v2:
> - Based the detection on the CM version and not on a single CPU version
> - Renamed the macro accordingly
> - Link to v1: https://lore.kernel.org/r/20240719-smp_i6500-v1-1-8738e67d4802@xxxxxxxxxxx
> ---
> arch/mips/include/asm/mips-cm.h | 4 ++++
> arch/mips/kernel/smp-cps.c | 5 ++++-
> 2 files changed, 8 insertions(+), 1 deletion(-)
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
