"Jiaxun Yang" <jiaxun.yang@xxxxxxxxxxx> writes: > 在2024年7月19日七月 下午10:14，Gregory CLEMENT写道： >> Unlike most other MIPS CPUs, the I6500 CPUs have different address >> offsets for the Global CSR Access Privilege register. In the "MIPS64 >> I6500 Multiprocessing System Programmer's Guide," it is stated that >> "the Global CSR Access Privilege register is located at offset 0x0120" >> in section 5.4. >> >> However, this is not the case for other MIPS64 CPUs such as the >> P6600. In the "MIPS64® P6600 Multiprocessing System Software User's >> Guide," section 6.4.2.6 states that the GCR_ACCESS register has an >> offset of 0x0020. > > Hi Gregory, > > I confirmed this is a CM3 feature rather than CPU core (Samruai) feature. > > Please use CM version to select register region. > (And perhaps Cc stable for this patch?) Actually, from my experience, the "Fixes:" tag is enough. The stable teams (and their bots) extensively backport patches from the Linus tree. Gregory
