On Wed, Mar 20, 2024 at 11:22:00PM +0800, Songyang Li wrote:
> The standard PCIe configuration read-write interface is used to
> access the configuration space of the peripheral PCIe devices
> of the mips processor after the PCIe link surprise down, it can
> generate kernel panic caused by "Data bus error". So it is
> necessary to add PCIe link status check for system protection.
> When the PCIe link is down or in training, assigning a value
> of 0 to the configuration address can prevent read-write behavior
> to the configuration space of peripheral PCIe devices, thereby
> preventing kernel panic.
>
> Signed-off-by: Songyang Li <leesongyang@xxxxxxxxxxx>
> ---
> arch/mips/pci/pcie-octeon.c | 6 ++++++
> 1 file changed, 6 insertions(+)
> mode change 100644 => 100755 arch/mips/pci/pcie-octeon.c
>
> diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
> old mode 100644
> new mode 100755
> index 2583e318e8c6..b080c7c6cc46
> --- a/arch/mips/pci/pcie-octeon.c
> +++ b/arch/mips/pci/pcie-octeon.c
> @@ -230,12 +230,18 @@ static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
> {
> union cvmx_pcie_address pcie_addr;
> union cvmx_pciercx_cfg006 pciercx_cfg006;
> + union cvmx_pciercx_cfg032 pciercx_cfg032;
>
> pciercx_cfg006.u32 =
> cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
> if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
> return 0;
>
> + pciercx_cfg032.u32 =
> + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
> + if ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1))
> + return 0;
> +
> pcie_addr.u64 = 0;
> pcie_addr.config.upper = 2;
> pcie_addr.config.io = 1;
> --
> 2.34.1
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
