Hi, We replace fixed clocks as declared in the initial platform support series [1] by read-only clocks exposed by the clock driver implemented here. Write-ability is supported by the hardware but not implemented, it could be added later-on if the need appears. We expose ten PLLs that derive directly from the main crystal. Also, a divider clock is exposed as a child clock of one of the PLLs. The platform devicetree has many more clock nodes but those are fixed-factors that are not hardware controllable; we therefore do not deal with them. This series starts with a fix for a fixed-rate clock registering macro that is broken. We are the first upstream users which explains why we found the typo. We end our patch series by adding the clock controller node to the platform devicetree & by replacing hardcoded devicetree clocks by the ones exposed by this driver. The controller driver addition is split in two commits to simplify reviewing. [1]: https://lore.kernel.org/lkml/20231212163459.1923041-1-gregory.clement@xxxxxxxxxxx/ Have a nice day, Théo Lebrun Signed-off-by: Théo Lebrun <theo.lebrun@xxxxxxxxxxx> --- Théo Lebrun (5): clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw dt-bindings: clock: mobileye,eyeq5-clk: add bindings clk: eyeq5: add controller clk: eyeq5: add OSPI table-based divider clock MIPS: mobileye: eyeq5: add OLB clocks controller node & pinmux nodes .../bindings/clock/mobileye,eyeq5-clk.yaml | 83 +++++ MAINTAINERS | 3 + .../{eyeq5-fixed-clocks.dtsi => eyeq5-clocks.dtsi} | 56 +--- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 9 +- drivers/clk/Kconfig | 11 + drivers/clk/Makefile | 1 + drivers/clk/clk-eyeq5.c | 346 +++++++++++++++++++++ include/dt-bindings/clock/mobileye,eyeq5-clk.h | 22 ++ include/linux/clk-provider.h | 4 +- 9 files changed, 493 insertions(+), 42 deletions(-) --- base-commit: 0bb6b85cadabf93a754df740bd1b6c56ef41ac2c change-id: 20231023-mbly-clk-87ce5c241f08 Best regards, -- Théo Lebrun <theo.lebrun@xxxxxxxxxxx>
