On Wed, Jul 05, 2023 at 11:08:31PM +0000, Thinh Nguyen wrote:
> On Sun, Jul 02, 2023, Ladislav Michl wrote:
> > From: Ladislav Michl <ladis@xxxxxxxxxxxxxx>
> >
> > Make dwc3_octeon_clocks_start just start the clocks.
>
> This commit message is different than the subject. Also, please explain
> why we need to move this logic to probe in this commit message body.
>
> >
> > Signed-off-by: Ladislav Michl <ladis@xxxxxxxxxxxxxx>
> > ---
> > CHANGES:
> > -v2: if else block bracket according CodingStyle
> >
> > drivers/usb/dwc3/dwc3-octeon.c | 148 ++++++++++++++++-----------------
> > 1 file changed, 71 insertions(+), 77 deletions(-)
> >
> > diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c
> > index 8d5facd881c1..668f6d3490b1 100644
> > --- a/drivers/usb/dwc3/dwc3-octeon.c
> > +++ b/drivers/usb/dwc3/dwc3-octeon.c
> > @@ -300,67 +300,14 @@ static int dwc3_octeon_config_power(struct device *dev, void __iomem *base)
> > return 0;
> > }
> >
> > -static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base)
> > +static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base,
> > + int ref_clk_sel, int ref_clk_fsel,
> > + int mpll_mul)
> > {
> > - int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2;
> > - u32 clock_rate;
> > + int div;
> > u64 val;
> > void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL;
> >
> > - if (dev->of_node) {
> > - const char *ss_clock_type;
> > - const char *hs_clock_type;
> > -
> > - i = of_property_read_u32(dev->of_node,
> > - "refclk-frequency", &clock_rate);
> > - if (i) {
> > - dev_err(dev, "No UCTL \"refclk-frequency\"\n");
> > - return -EINVAL;
> > - }
> > - i = of_property_read_string(dev->of_node,
> > - "refclk-type-ss", &ss_clock_type);
> > - if (i) {
> > - dev_err(dev, "No UCTL \"refclk-type-ss\"\n");
> > - return -EINVAL;
> > - }
> > - i = of_property_read_string(dev->of_node,
> > - "refclk-type-hs", &hs_clock_type);
> > - if (i) {
> > - dev_err(dev, "No UCTL \"refclk-type-hs\"\n");
> > - return -EINVAL;
> > - }
> > - if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
> > - if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0)
> > - ref_clk_sel = 0;
> > - else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
> > - ref_clk_sel = 2;
> > - else
> > - dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n",
> > - hs_clock_type);
> > - } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
> > - if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0)
> > - ref_clk_sel = 1;
> > - else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
> > - ref_clk_sel = 3;
> > - else {
> > - dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n",
> > - hs_clock_type);
> > - ref_clk_sel = 3;
> > - }
> > - } else
> > - dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n",
> > - ss_clock_type);
> > -
> > - if ((ref_clk_sel == 0 || ref_clk_sel == 1) &&
> > - (clock_rate != 100000000))
> > - dev_warn(dev, "Invalid UCTL clock rate of %u, using 100000000 instead\n",
> > - clock_rate);
> > -
> > - } else {
> > - dev_err(dev, "No USB UCTL device node\n");
> > - return -EINVAL;
> > - }
> > -
> > /*
> > * Step 1: Wait for all voltages to be stable...that surely
> > * happened before starting the kernel. SKIP
> > @@ -404,24 +351,6 @@ static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base)
> > val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL;
> > val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel);
> >
> > - ref_clk_fsel = 0x07;
> > - switch (clock_rate) {
> > - default:
> > - dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n",
> > - clock_rate);
> > - fallthrough;
> > - case 100000000:
> > - mpll_mul = 0x19;
> > - if (ref_clk_sel < 2)
> > - ref_clk_fsel = 0x27;
> > - break;
> > - case 50000000:
> > - mpll_mul = 0x32;
> > - break;
> > - case 125000000:
> > - mpll_mul = 0x28;
> > - break;
> > - }
> > val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL;
> > val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel);
> >
> > @@ -505,8 +434,72 @@ static void __init dwc3_octeon_phy_reset(void __iomem *base)
> > static int dwc3_octeon_probe(struct platform_device *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > + struct device_node *node = dev->of_node;
> > struct dwc3_data *data;
> > - int err;
> > + int err, ref_clk_sel, ref_clk_fsel, mpll_mul;
> > + uint32_t clock_rate;
>
> Use u32?
I do not like homebrew types when we have standard ones. But it seems almost
all usb code is using u32, so I can live with that.
> > + const char *hs_clock_type, *ss_clock_type;
> > +
> > + if (!node) {
> > + dev_err(dev, "No USB UCTL device node\n");
> > + return -EINVAL;
> > + }
> > +
> > + if (of_property_read_u32(node, "refclk-frequency", &clock_rate)) {
> > + dev_err(dev, "No UCTL \"refclk-frequency\"\n");
> > + return -EINVAL;
> > + }
> > + if (of_property_read_string(node, "refclk-type-ss", &ss_clock_type)) {
> > + dev_err(dev, "No UCTL \"refclk-type-ss\"\n");
> > + return -EINVAL;
> > + }
> > + if (of_property_read_string(node, "refclk-type-hs", &hs_clock_type)) {
> > + dev_err(dev, "No UCTL \"refclk-type-hs\"\n");
> > + return -EINVAL;
> > + }
> > +
> > + ref_clk_sel = 2;
> > + if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
> > + if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0)
> > + ref_clk_sel = 0;
> > + else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
> > + ref_clk_sel = 2;
> > + else
> > + dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n",
> > + hs_clock_type);
> > + } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
>
> Did you run checkpatch? I still see some minor formatting issues.
Yes I did. What complain do you see from checkpatch?
> > + if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0)
> > + ref_clk_sel = 1;
> > + else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) {
> > + ref_clk_sel = 3;
> > + } else {
> > + dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n",
> > + hs_clock_type);
> > + ref_clk_sel = 3;
> > + }
> > + } else {
> > + dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n",
> > + ss_clock_type);
> > + }
> > +
> > + ref_clk_fsel = 0x07;
> > + switch (clock_rate) {
> > + default:
> > + dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n",
> > + clock_rate);
> > + fallthrough;
> > + case 100000000:
> > + mpll_mul = 0x19;
> > + if (ref_clk_sel < 2)
> > + ref_clk_fsel = 0x27;
> > + break;
> > + case 50000000:
> > + mpll_mul = 0x32;
> > + break;
> > + case 125000000:
> > + mpll_mul = 0x28;
> > + break;
> > + }
> >
> > data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> > if (!data)
> > @@ -516,7 +509,8 @@ static int dwc3_octeon_probe(struct platform_device *pdev)
> > if (IS_ERR(data->base))
> > return PTR_ERR(data->base);
> >
> > - err = dwc3_octeon_clocks_start(dev, data->base);
> > + err = dwc3_octeon_clocks_start(dev, data->base,
> > + ref_clk_sel, ref_clk_fsel, mpll_mul);
> > if (err)
> > return err;
> >
> > --
> > 2.39.2
> >
>
> BR,
> Thinh
