On Sun, Jun 04, 2023 at 02:26:52PM +0200, Paul Cercueil wrote: > From: Siarhei Volkau <lis8215@xxxxxxxxx> > > The LXW, LXH, LXHU opcodes are part of the MXU ASE found in Ingenic > XBurst based SoCs. > > While technically part of the MXU ASE, they do not touch any of the SIMD > registers, and can be used even when the MXU ASE is disabled. > > This patch makes it possible to emulate unaligned access for those > instructions. > > Signed-off-by: Siarhei Volkau <lis8215@xxxxxxxxx> > --- > arch/mips/include/uapi/asm/inst.h | 33 +++++++++++++++++++++++++ > arch/mips/kernel/unaligned.c | 41 +++++++++++++++++++++++++++++++ > 2 files changed, 74 insertions(+) applied to mips-next. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]
