пн, 17 окт. 2022 г. в 20:24, Paul Cercueil <paul@xxxxxxxxxxxxxxx>:
>
>
>
> Le lun., oct. 17 2022 at 20:10:56 +0300, Siarhei Volkau
> <lis8215@xxxxxxxxx> a écrit :
> > пн, 17 окт. 2022 г. в 12:24, Paul Cercueil
> > <paul@xxxxxxxxxxxxxxx>:
> >
> >> > + [JZ4755_CLK_AIC] = {
> >> > + "aic", CGU_CLK_GATE,
> >> > + .parents = { JZ4755_CLK_I2S, -1, -1, -1 },
> >>
> >> Wrong parent here, should be JZ4755_CLK_EXT_HALF.
> >
> > I don't agree, see Figure 20-13 in the JZ4755 PM.
>
> 20-13 describes the I2S clock, no?
See 20.4.9 Serial Audio Clocks and Sampling Frequencies.
It stated that: "For internal CODEC ... CODEC needs a 12MHz
clock from CPM called SYS_CLK ...", but SYS_CLK is described
only in the I2S Controller section. I assume it is the same clock.
>
> AIC clock's parent is EXT/2 according to the diagram in 8.2.2.
>
It's a bit cryptic manual, who knows how it's done in the HW.
I observed that codec runs on a desired sample rate only when PLL
equals 432 or 216 MHz, but SYS_CLK is definitely configured to be
12MHz - from EXTCLK. On other PLL frequencies it is lower by
2-4% than expected. That isn't observed on JZ4725B.
> >> Well it would be good to know...
> >
> > Indeed, I will try to figure it out.
>
> Cheers,
> -Paul
>
>
