Re: [PATCH v2 4/4] clk: Add Ingenic JZ4755 CGU driver

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Le lun., oct. 17 2022 at 20:10:56 +0300, Siarhei Volkau <lis8215@xxxxxxxxx> a écrit :
пн, 17 окт. 2022 г. в 12:24, Paul Cercueil <paul@xxxxxxxxxxxxxxx>:

 > +     [JZ4755_CLK_AIC] = {
 > +             "aic", CGU_CLK_GATE,
 > +             .parents = { JZ4755_CLK_I2S, -1, -1, -1 },

 Wrong parent here, should be JZ4755_CLK_EXT_HALF.

I don't  agree, see Figure 20-13 in the JZ4755 PM.

20-13 describes the I2S clock, no?

AIC clock's parent is EXT/2 according to the diagram in 8.2.2.

 Well it would be good to know...

Indeed, I will try to figure it out.

Cheers,
-Paul






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