On Wednesday 03 November 2021 14:49:07 Maciej W. Rozycki wrote: > On Tue, 2 Nov 2021, Pali Rohár wrote: > > > Hello Maciej! Thank you very much for the explanation! > > You are welcome! > > > I'm surprised that Marvell copied this 20 years old MIPS Galileo PCI > > logic into followup ARM SoC PCIe IPs (and later also into recent ARM64 > > A3720 SoC PCIe IP), removed configuration of PCI class code via > > strapping pins and let default PCI class code value to Memory device, > > even also when PCIe controller is running in Root Complex mode. And so > > correction can be done only from "CPU bus". > > Still the bootstrap firmware (say U-boot, as I can see it mentioned in > your reference) can write the correct value to the class code register. > Or can it? Yes, it can. And I have already sent patches to do it.
