On Mon, Feb 08, 2021 at 04:57:33PM +0100, Maciej W. Rozycki wrote:
> > diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
> > index e98cc977a735b2..f8c9663e7faa10 100644
> > --- a/arch/mips/mti-malta/malta-setup.c
> > +++ b/arch/mips/mti-malta/malta-setup.c
> > @@ -143,7 +143,7 @@ static void __init plat_setup_iocoherency(void)
> > pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
> > }
> >
> > - if (supported)
> > + if (supported) {
> > if (dma_force_noncoherent) {
> > pr_info("Hardware DMA cache coherency disabled\n");
> > return;
>
> I think this has to go with 1/6; otherwise compilation breaks between
> then and now AFAICT.
Indeed.
> Do you need to have this verified anyhow? I only have a non-coherent 5Kc
> Malta though.
If you get a chance to test this logic, that would be great.
