On Mon, 8 Feb 2021, Christoph Hellwig wrote: > diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c > index e98cc977a735b2..f8c9663e7faa10 100644 > --- a/arch/mips/mti-malta/malta-setup.c > +++ b/arch/mips/mti-malta/malta-setup.c > @@ -143,7 +143,7 @@ static void __init plat_setup_iocoherency(void) > pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); > } > > - if (supported) > + if (supported) { > if (dma_force_noncoherent) { > pr_info("Hardware DMA cache coherency disabled\n"); > return; I think this has to go with 1/6; otherwise compilation breaks between then and now AFAICT. Do you need to have this verified anyhow? I only have a non-coherent 5Kc Malta though. Maciej