On 14/01/2021 00:13, Jiaxun Yang wrote:
range->fwnode = &of_root->fwnode;
+ range->size = MMIO_LOWER_RESERVED;
+ range->hw_start = LOONGSON_PCIIO_BASE;
+ range->flags = LOGIC_PIO_CPU_MMIO;
+
+ if (logic_pio_register_range(range)) {
+ pr_err("Failed to reserve PIO range for legacy ISA\n");
+ goto free_range;
+ }
Hi Jiaxun,
+
+ if (WARN(range->io_start != 0,
+ "Reserved PIO range does not start from 0\n"))
Do the mips code still rely on this check?
Hi Jiaxun,
Yes :-/
ok, but I was hoping that this dependency would be removed at some stage.
I was considering changing the logical PIO code to reserve the first
64K of PCI MMIO space, but making that change would break this code as
things stand.
The motivation is that some drivers, like [0], access IO ports
unconditionally and can kill systems when no PCI host exists. By
reserving the first 64K, accesses by those drivers could nullified.
Actually we're trying to deal with almost the same problem.
The reserved region on MIPS is used to serve these driver that access
I/O ports bypassing resource subsystem.
Yes, so reserving the first 64K of IO space would break mips, as things
stand. Has any work been done for these drivers that bypass resource
subsystem (or directly access hardcoded IO ports)?
I may just do this (reserve 64K) under INDIRECT_PIO for now, not sure yet.
Thanks,
John
