Hi, all,
On Tue, Sep 1, 2020 at 2:53 PM Huang Pei <huangpei@xxxxxxxxxxx> wrote:
>
> In cc97ab235f ("MIPS: Simplify FP context initialization), init_fp_ctx
> just initialize the fp/msa context, and own_fp_inatomic just restore
> FCSR and 64bit FP regs from it, but miss MSACSR and upper MSA regs for
> MSA, so MSACSR and MSA upper regs's value from previous task on current
> cpu can leak into current task and cause unpredictable behavior when MSA
> context not initialized.
>
I still think this needs an ACK from Paul Burton.
Huacai
> Fixes: cc97ab235f ("MIPS: Simplify FP context initialization")
> Signed-off-by: Huang Pei <huangpei@xxxxxxxxxxx>
> ---
> arch/mips/kernel/traps.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index 38aa07ccdbcc..cf788591f091 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
> @@ -1287,6 +1287,18 @@ static int enable_restore_fp_context(int msa)
> err = own_fpu_inatomic(1);
> if (msa && !err) {
> enable_msa();
> + /*
> + * with MSA enabled, userspace can see MSACSR
> + * and MSA regs, but the values in them are from
> + * other task before current task, restore them
> + * from saved fp/msa context
> + */
> + write_msa_csr(current->thread.fpu.msacsr);
> + /*
> + * own_fpu_inatomic(1) just restore low 64bit,
> + * fix the high 64bit
> + */
> + init_msa_upper();
> set_thread_flag(TIF_USEDMSA);
> set_thread_flag(TIF_MSA_CTX_LIVE);
> }
> --
> 2.17.1
>
