On Thu, Jul 30, 2020 at 01:06:03PM +0100, Marc Zyngier wrote: > On Thu, 30 Jul 2020 16:51:25 +0800, Huacai Chen wrote: > > Modernized Loongson64 platforms use a hierarchical interrupt controller > > architecture. For LS7A PCH, the hierarchy (from inside to outside) is > > CPUINTC --> LIOINTC --> HTVEC --> PCHPIC/PCHMSI. However, the current > > status is that there are several bugs in the LIOINTC and PCHPIC drivers, > > and the HTVEC driver should be improved to support 8 groups of vectors. > > Loonson64C support only 4 groups of HT vectors, and Loongson64G support > > as many as 8 groups, so the .dts file and dt-bindings description should > > also be updated. > > > > [...] > > Applied to irq/irqchip-next, thanks! > > [1/5] dt-bindings: interrupt-controller: Update Loongson HTVEC description > commit: 8fea4b2e804ab8ff93bd0d67a3dadee1d1a3e24f > [3/5] irqchip/loongson-liointc: Fix misuse of gc->mask_cache > commit: c9c73a05413ea4a465cae1cb3593b01b190a233f > [4/5] irqchip/loongson-htvec: Support 8 groups of HT vectors > commit: c47e388cfc648421bd821f5d9fda9e76eefe29cd > [5/5] irqchip/loongson-pch-pic: Fix the misused irq flow handler > commit: ac62460c24126eb2442e3653a266ebbf05b004d8 > > Please note that I haven't taken patch #2, as it doesn't apply on top > of irqchip/next. Please route it via the MIPS tree. I'll take it. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]
