Modernized Loongson64 platforms use a hierarchical interrupt controller architecture. For LS7A PCH, the hierarchy (from inside to outside) is CPUINTC --> LIOINTC --> HTVEC --> PCHPIC/PCHMSI. However, the current status is that there are several bugs in the LIOINTC and PCHPIC drivers, and the HTVEC driver should be improved to support 8 groups of vectors. Loonson64C support only 4 groups of HT vectors, and Loongson64G support as many as 8 groups, so the .dts file and dt-bindings description should also be updated. V1 -> V2: 1, Add a cover letter. 2, Add Reviewed-by and Tested-by tags. 3, Improve commit messages by adding Fixes: tags. Huacai Chen(5): dt-bindings: interrupt-controller: Update Loongson HTVEC description MIPS: DTS: Fix number of msi vectors for Loongson64G irqchip: loongson-liointc: Fix misuse of gc->mask_cache irqchip: loongson-htvec: Support 8 groups of HT vectors irqchip: loongson-pch-pic: Fix the misused irq flow handler Signed-off-by: Huacai Chen <chenhc@xxxxxxxxxx> --- .../interrupt-controller/loongson,htvec.yaml | 4 ++-- .../boot/dts/loongson/loongson64g_4core_ls7a.dts | 8 ++++++-- drivers/irqchip/irq-loongson-htvec.c | 22 ++++++++++------------ drivers/irqchip/irq-loongson-liointc.c | 10 +++++----- drivers/irqchip/irq-loongson-pch-pic.c | 15 ++++----------- 5 files changed, 27 insertions(+), 32 deletions(-) -- 2.7.0
