This register is named GSCause in Loongson manuals. It carries Loongson extended exception information. Reviewed-by: Huacai Chen <chenhc@xxxxxxxxxx> Signed-off-by: WANG Xuerui <git@xxxxxxxxxx> Cc: Huacai Chen <chenhc@xxxxxxxxxx> Cc: Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> Cc: Tiezhu Yang <yangtiezhu@xxxxxxxxxxx> --- arch/mips/include/asm/mipsregs.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 11094d857b92..5ba268266d16 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -86,6 +86,7 @@ #define CP0_XCONTEXT $20 #define CP0_FRAMEMASK $21 #define CP0_DIAGNOSTIC $22 +#define CP0_DIAGNOSTIC1 $22, 1 #define CP0_DEBUG $23 #define CP0_DEPC $24 #define CP0_PERFORMANCE $25 @@ -1051,6 +1052,13 @@ /* Flush FTLB */ #define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13) +/* + * Diag1 (GSCause in Loongson-speak) fields + */ +/* Loongson-specific exception code (GSExcCode) */ +#define LOONGSON_DIAG1_EXCCODE_SHIFT 2 +#define LOONGSON_DIAG1_EXCCODE GENMASK(6, 2) + /* CvmCtl register field definitions */ #define CVMCTL_IPPCI_SHIFT 7 #define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT) -- 2.25.1
