RE: [DVB] CXD2099 - Question about the CAM clock

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> 
> I managed to find a series of values that are working correctly for MCLKI:
> 
> MCLKI = 0x5554 - i * 0x0c
> 
> In my case I can go down to 0x5338 before having TS errors.
> 

>From CXD2099 specs
--
It is a requirement for the frequency of MCLKI to be set higher than the input
data rate. ie 8
times TICLK. If this condition is not met then the internal buffer will
overflow and the register
TSIN_FIFO_OVFL is set to 1. This register should be read at regular intervals
to ensure reliable
operation.
--

Watch out that you're not slowly overflowing the internal buffer if MCLKI is
not fast enough...

Are you working with the ddbridge ?

--
Issa

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