On Wed, 23 Feb 2011, Hans Verkuil wrote: > On Wednesday, February 23, 2011 15:06:49 Aguirre, Sergio wrote: > > Guennadi and Hans, > > > > <snip> > > > > > > The only static data I am concerned about are those that affect signal > > > integrity. > > > > After thinking carefully about this I realized that there is really only > > > one > > > > setting that is relevant to that: the sampling edge. The polarities do > > > not > > > > matter in this. > > > > I respectfully disagree. > > > > AFAIK, There is not such thing as sampling edge configuration for MIPI > > Receivers, and the polarities DO matter, since it's a differential > > signal. > > The polarities do not matter for a standard parallel bus. I cannot speak for > MIPI or CSI busses as I have no experience there. So if you say that > polarities matter for MIPI, then for MIPI those should be specified statically > as well. Do I misunderstand? I interpreted Hans' proposal as: clock edge sensitivity is critical mainly because of high frequency, at which the signal integrity is harder to maintain, and therefore we cannot rely on automagic. Whereas sync signals are much lower frequency, and therefore any breakage would be easier to detect. I don't otherwise understand what "polarities do not matter" mean - of course they do. What am I missing? Thanks Guennadi --- Guennadi Liakhovetski, Ph.D. Freelance Open-Source Software Developer http://www.open-technology.de/ -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
