On Wednesday, February 23, 2011 09:10:42 Hans Verkuil wrote: > Unfortunately, if a subdev is set to 'sample at rising edge', then that does > not necessarily mean that the host should sample at the same edge. Depending > on the clock line routing and the integrity of the clock signal the host may > actually have to sample on the other edge. And yes, I've seen this. It might be useful to give some background information regarding the sampling edge problems. There are two main reasons why the sampling edge can be hardware dependent. The first is if the data lines go through an amplifier or something similar that will slightly delay the data lines compared to the clock signal. This can shift the edge at which you have to sample. Actually, this may even be dependent on the clock frequency. I have not seen that in real life yet, but it might happen. This will complicate things even more since in that case you need to make a callback function in the board code that determines the sampling edge based on the clock frequency. I think we can ignore that for now, but we do need to keep it in mind. The other is the waveform of the clock. For relatively low frequencies this will resemble a symmetrical square wave. But for higher frequencies this more resembles the bottom waveform in this picture: http://myweb.msoe.edu/williamstm/Images/Divider2.jpg This is asymmetric so depending on the slopes the sampling edge can make quite a difference. The higher the clock frequency, the more asymmetric the waveform will look. Regards, Hans -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
