Hi Biju,
On Mon, 10 Feb 2025 at 12:54, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > -----Original Message-----
> > From: Tommaso Merciai <tomm.merciai@xxxxxxxxx>
> > Sent: 10 February 2025 11:46
> > Subject: [PATCH 1/8] clk: renesas: r9a09g047: Add support for CRU0 clocks, and resets
> >
> > Add support for CRU0 clocks and resets along with the corresponding divider.
> >
> > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>
> > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> > @@ -49,6 +53,12 @@ static const struct clk_div_table dtable_1_8[] = {
> > {0, 0},
> > };
> >
> > +static const struct clk_div_table dtable_2_4[] = {
> > + {0, 2},
> > + {1, 4},
> > + {0, 0},
>
> Not sure {0, 2}, {1, 4}, {0, 0}, to make lines shorter?
All SoCs from the RZ/G2L and RZ/V2H families use this formatting style:
git grep -wW clk_div_table -- drivers/clk/renesas/r9a0*
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
