Hi,
I'm sorry for this bad send, please dismiss.
Le lundi 17 février 2025 à 16:00 -0500, Nicolas Dufresne a écrit :
> The desired clock frequency was correctly set to 400MHz in the device tree
> but was lowered by the driver to 300MHz breaking 4K 60Hz content playback.
> Fix the issue by removing the driver call to clk_set_rate(), which reduce
> the amount of board specific code.
>
> Fixes: 003afda97c65 ("media: verisilicon: Enable AV1 decoder on rk3588")
> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@xxxxxxxxxxxxx>
> ---
> This patch fixes user report of AV1 4K60 decoder not being fast enough
> on RK3588 based SoC. This is a break from Hantro original authors
> habbit of coding the frequencies in the driver instead of specifying this
> frequency in the device tree. The other calls to clk_set_rate() are left
> since this would require modifying many dtsi files, which would then be
> unsuitable for backport.
> ---
> drivers/media/platform/verisilicon/rockchip_vpu_hw.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
> index 964122e7c355934cd80eb442219f6ba51bba8b71..9d8eab33556d62733ec7ec6b5e685c86ba7086e4 100644
> --- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
> +++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
> @@ -17,7 +17,6 @@
>
> #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)
> #define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
> -#define RK3588_ACLK_MAX_FREQ (300 * 1000 * 1000)
>
> #define ROCKCHIP_VPU981_MIN_SIZE 64
>
> @@ -440,10 +439,9 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
> return 0;
> }
>
> +/* TODO just remove, the CLK are defined correctly in the DTS */
> static int rk3588_vpu981_hw_init(struct hantro_dev *vpu)
Obviously that function is meant to completely go away, got distracted
and sent the old version.
Nicolas
> {
> - /* Bump ACLKs to max. possible freq. to improve performance. */
> - clk_set_rate(vpu->clocks[0].clk, RK3588_ACLK_MAX_FREQ);
> return 0;
> }
>
> @@ -807,7 +805,6 @@ const struct hantro_variant rk3588_vpu981_variant = {
> .codec_ops = rk3588_vpu981_codec_ops,
> .irqs = rk3588_vpu981_irqs,
> .num_irqs = ARRAY_SIZE(rk3588_vpu981_irqs),
> - .init = rk3588_vpu981_hw_init,
> .clk_names = rk3588_vpu981_vpu_clk_names,
> .num_clocks = ARRAY_SIZE(rk3588_vpu981_vpu_clk_names)
> };
>
> ---
> base-commit: 2014c95afecee3e76ca4a56956a936e23283f05b
> change-id: 20250217-b4-hantro-av1-clock-rate-e5497f1499df
>
> Best regards,
