On 21.06.2024 11:40 AM, George Chan via B4 Relay wrote:
> From: George Chan <gchan9527@xxxxxxxxx>
>
> This commit describes the hardware layout for the sc7180 for the
> following hardware blocks:
>
> - 2 x VFE
> - 1 x VFE Lite
> - 2 x CSID
> - 1 x CSID Lite
> - 4 x CSI PHY
>
> Signed-off-by: George Chan <gchan9527@xxxxxxxxx>
> ---
[...]
> if (ret) {
> - dev_err(dev, "clock enable failed: %d\n", ret);
> + dev_err(dev, "clock enable failed: %s %d\n", clock[i].name, ret);
This is a good change, but should be separate
Generally this looks quite in line with [1], although I wasn't able to find
the matching clock rates
Konrad
[1] https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/blob/UC.UM.1.0.r1-02500-sa8155.0/arch/arm64/boot/dts/qcom/atoll-camera.dtsi
