From: George Chan <gchan9527@xxxxxxxxx>
This commit describes the hardware layout for the sc7180 for the
following hardware blocks:
- 2 x VFE
- 1 x VFE Lite
- 2 x CSID
- 1 x CSID Lite
- 4 x CSI PHY
Signed-off-by: George Chan <gchan9527@xxxxxxxxx>
---
drivers/media/platform/qcom/camss/camss.c | 218 +++++++++++++++++++++++++++++-
1 file changed, 217 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 1923615f0eea..d50f98565531 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -713,6 +713,210 @@ static const struct camss_subdev_resources vfe_res_845[] = {
}
};
+static const struct camss_subdev_resources csiphy_res_7180[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = {},
+ .clock = {
+ "csiphy0",
+ "csiphy0_timer"
+ },
+ .clock_rate = {
+ { 150000000, 270000000, 360000000 },
+ { 300000000 },
+ },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .ops = &csiphy_ops_3ph_1_0
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = {},
+ .clock = {
+ "csiphy1",
+ "csiphy1_timer"
+ },
+ .clock_rate = {
+ { 150000000, 270000000, 360000000 },
+ { 300000000 },
+ },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .ops = &csiphy_ops_3ph_1_0
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = {},
+ .clock = {
+ "csiphy2",
+ "csiphy2_timer"
+ },
+ .clock_rate = {
+ { 150000000, 270000000, 360000000 },
+ { 300000000 },
+ },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .ops = &csiphy_ops_3ph_1_0
+ },
+ /* CSIPHY3 */
+ {
+ .regulators = {},
+ .clock = {
+ "csiphy3",
+ "csiphy3_timer"
+ },
+ .clock_rate = {
+ { 150000000, 270000000, 360000000 },
+ { 300000000 },
+ },
+ .reg = { "csiphy3" },
+ .interrupt = { "csiphy3" },
+ .ops = &csiphy_ops_3ph_1_0
+ }
+};
+
+static const struct camss_subdev_resources csid_res_7180[] = {
+ /* CSID0 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+ .clock = {
+ "soc_ahb",
+ "vfe0",
+ "vfe0_cphy_rx",
+ "csi0"
+ },
+ .clock_rate = {
+ { 0 },
+ { 240000000, 360000000, 432000000, 600000000 },
+ { 150000000, 270000000, 360000000 },
+ { 150000000, 270000000, 360000000, 480000000 },
+ },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .ops = &csid_ops_gen2
+ },
+
+ /* CSID1 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+ .clock = {
+ "soc_ahb",
+ "vfe1",
+ "vfe1_cphy_rx",
+ "csi1",
+ },
+ .clock_rate = {
+ { 0 },
+ { 240000000, 360000000, 432000000, 600000000 },
+ { 150000000, 270000000, 360000000 },
+ { 150000000, 270000000, 360000000, 480000000 },
+ },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .ops = &csid_ops_gen2
+ },
+
+ /* CSID2 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+ .clock = {
+ "soc_ahb",
+ "vfe_lite",
+ "vfe_lite_cphy_rx",
+ "csi2",
+ },
+ .clock_rate = {
+ { 0 },
+ { 240000000, 360000000, 432000000, 600000000 },
+ { 150000000, 270000000, 360000000 },
+ { 150000000, 270000000, 360000000, 480000000 },
+ },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .is_lite = true,
+ .ops = &csid_ops_gen2
+ }
+};
+
+static const struct camss_subdev_resources vfe_res_7180[] = {
+ /* VFE0 */
+ {
+ .regulators = {},
+ .clock = {
+ "camnoc_axi",
+ "cpas_ahb",
+ "soc_ahb",
+ "vfe0",
+ "vfe0_axi",
+ "csi0",
+ },
+ .clock_rate = {
+ { 0 },
+ { 0 },
+ { 0 },
+ { 19200000, 240000000, 360000000, 432000000, 600000000 },
+ { 0 },
+ { 150000000, 270000000, 360000000, 480000000 },
+ },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .pd_name = "ife0",
+ .line_num = 4,
+ .has_pd = true,
+ .ops = &vfe_ops_170
+ },
+ /* VFE1 */
+ {
+ .regulators = {},
+ .clock = {
+ "camnoc_axi",
+ "cpas_ahb",
+ "soc_ahb",
+ "vfe1",
+ "vfe1_axi",
+ "csi1",
+ },
+ .clock_rate = {
+ { 0 },
+ { 0 },
+ { 0 },
+ { 19200000, 240000000, 360000000, 432000000, 600000000 },
+ { 0 },
+ { 150000000, 270000000, 360000000, 480000000 },
+ },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .pd_name = "ife1",
+ .line_num = 4,
+ .has_pd = true,
+ .ops = &vfe_ops_170
+ },
+ /* VFE-lite */
+ {
+ .regulators = {},
+ .clock = {
+ "camnoc_axi",
+ "cpas_ahb",
+ "soc_ahb",
+ "vfe_lite",
+ "csi2",
+ },
+ .clock_rate = {
+ { 0 },
+ { 0 },
+ { 0 },
+ { 19200000, 240000000, 360000000, 432000000, 600000000 },
+ { 150000000, 270000000, 360000000, 480000000 },
+ },
+ .reg = { "vfe_lite" },
+ .interrupt = { "vfe_lite" },
+ .is_lite = true,
+ .line_num = 4,
+ .ops = &vfe_ops_170
+ }
+};
+
static const struct camss_subdev_resources csiphy_res_8250[] = {
/* CSIPHY0 */
{
@@ -1263,7 +1467,7 @@ int camss_enable_clocks(int nclocks, struct camss_clock *clock,
for (i = 0; i < nclocks; i++) {
ret = clk_prepare_enable(clock[i].clk);
if (ret) {
- dev_err(dev, "clock enable failed: %d\n", ret);
+ dev_err(dev, "clock enable failed: %s %d\n", clock[i].name, ret);
goto error;
}
}
@@ -2105,6 +2309,17 @@ static const struct camss_resources sdm845_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_845),
};
+static const struct camss_resources sc7180_resources = {
+ .version = CAMSS_7180,
+ .pd_name = "top",
+ .csiphy_res = csiphy_res_7180,
+ .csid_res = csid_res_7180,
+ .vfe_res = vfe_res_7180,
+ .csiphy_num = ARRAY_SIZE(csiphy_res_7180),
+ .csid_num = ARRAY_SIZE(csid_res_7180),
+ .vfe_num = ARRAY_SIZE(vfe_res_7180),
+};
+
static const struct camss_resources sm8250_resources = {
.version = CAMSS_8250,
.pd_name = "top",
@@ -2137,6 +2352,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
{ .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
+ { .compatible = "qcom,sc7180-camss", .data = &sc7180_resources },
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
{ }
--
2.34.1
