Annotate the per mode register setting lists.
This is a preparation patch for moving to calculating the per mode
settings, allowing to set any mode through cropping.
The annotations make it easier to see which registers are mode
dependent and which are fixed.
Acked-by: Rui Miguel Silva <rmfrfs@xxxxxxxxx>
Reviewed-by: Daniel Scally <dan.scally@xxxxxxxxxxxxxxxx>
Signed-off-by: Hans de Goede <hdegoede@xxxxxxxxxx>
---
drivers/media/i2c/ov2680.c | 118 ++++++++++++++++++++++++++++++++-----
1 file changed, 104 insertions(+), 14 deletions(-)
diff --git a/drivers/media/i2c/ov2680.c b/drivers/media/i2c/ov2680.c
index a83efd449993..e7d2e555e1c6 100644
--- a/drivers/media/i2c/ov2680.c
+++ b/drivers/media/i2c/ov2680.c
@@ -140,27 +140,117 @@ static const int ov2680_hv_flip_bayer_order[] = {
};
static const struct reg_sequence ov2680_setting_30fps_QUXGA_800_600[] = {
- {0x3086, 0x01}, {0x370a, 0x23}, {0x3808, 0x03}, {0x3809, 0x20},
- {0x380a, 0x02}, {0x380b, 0x58}, {0x380c, 0x06}, {0x380d, 0xac},
- {0x380e, 0x02}, {0x380f, 0x84}, {0x3811, 0x04}, {0x3813, 0x04},
- {0x3814, 0x31}, {0x3815, 0x31}, {0x3820, 0xc0}, {0x4008, 0x00},
- {0x4009, 0x03}, {0x4837, 0x1e}, {0x3501, 0x4e}, {0x3502, 0xe0},
+ /* Set PLL SP DIV to 1 for binning mode */
+ {0x3086, 0x01},
+
+ /* Sensor control register 0x0a to 0x23 for binning mode */
+ {0x370a, 0x23},
+
+ /* Set X and Y output size to 800x600 */
+ {0x3808, 0x03},
+ {0x3809, 0x20},
+ {0x380a, 0x02},
+ {0x380b, 0x58},
+
+ /* Set HTS + VTS to 1708x644 */
+ {0x380c, 0x06},
+ {0x380d, 0xac},
+ {0x380e, 0x02},
+ {0x380f, 0x84},
+
+ /* Set ISP WIN X and Y start to 4x4 */
+ {0x3811, 0x04},
+ {0x3813, 0x04},
+
+ /* Set X INC and Y INC for binning */
+ {0x3814, 0x31},
+ {0x3815, 0x31},
+
+ /* Initialize FORMAT1 to default/reset value (vflip disabled) */
+ {0x3820, 0xc0},
+
+ /* Set black level compensation range to 0 - 3 (default 0 - 11) */
+ {0x4008, 0x00},
+ {0x4009, 0x03},
+
+ /* Set MIPI pclk period to 0x1e (default/reset is 0x18) */
+ {0x4837, 0x1e},
+
+ /* Initialize exposure to 0x4ee (overridden by the ctrl, drop this */
+ {0x3501, 0x4e},
+ {0x3502, 0xe0},
+
+ /* R MANUAL set exposure and gain to manual (hw does not do auto) */
{0x3503, 0x03},
};
static const struct reg_sequence ov2680_setting_30fps_720P_1280_720[] = {
- {0x3086, 0x00}, {0x3808, 0x05}, {0x3809, 0x00}, {0x380a, 0x02},
- {0x380b, 0xd0}, {0x380c, 0x06}, {0x380d, 0xa8}, {0x380e, 0x05},
- {0x380f, 0x0e}, {0x3811, 0x08}, {0x3813, 0x06}, {0x3814, 0x11},
- {0x3815, 0x11}, {0x3820, 0xc0}, {0x4008, 0x00},
+ /* Set PLL SP DIV to 0 for not binning mode */
+ {0x3086, 0x00},
+
+ /* Set X and Y output size to 1280x720 */
+ {0x3808, 0x05},
+ {0x3809, 0x00},
+ {0x380a, 0x02},
+ {0x380b, 0xd0},
+
+ /* Set HTS + VTS to 1704x1294 */
+ {0x380c, 0x06},
+ {0x380d, 0xa8},
+ {0x380e, 0x05},
+ {0x380f, 0x0e},
+
+ /* Set ISP WIN X and Y start to 8x6 */
+ {0x3811, 0x08},
+ {0x3813, 0x06},
+
+ /* Set X INC and Y INC for non binning */
+ {0x3814, 0x11},
+ {0x3815, 0x11},
+
+ /* Initialize FORMAT1 to default/reset value (vflip disabled) */
+ {0x3820, 0xc0},
+
+ /* Set backlight compensation range start to 0 */
+ {0x4008, 0x00},
};
static const struct reg_sequence ov2680_setting_30fps_UXGA_1600_1200[] = {
- {0x3086, 0x00}, {0x3501, 0x4e}, {0x3502, 0xe0}, {0x3808, 0x06},
- {0x3809, 0x40}, {0x380a, 0x04}, {0x380b, 0xb0}, {0x380c, 0x06},
- {0x380d, 0xa8}, {0x380e, 0x05}, {0x380f, 0x0e}, {0x3811, 0x00},
- {0x3813, 0x00}, {0x3814, 0x11}, {0x3815, 0x11}, {0x3820, 0xc0},
- {0x4008, 0x00}, {0x4837, 0x18}
+ /* Set PLL SP DIV to 0 for not binning mode */
+ {0x3086, 0x00},
+
+ /* Initialize exposure to 0x4ee (overridden by the ctrl, drop this */
+ {0x3501, 0x4e},
+ {0x3502, 0xe0},
+
+ /* Set X and Y output size to 1600x1200 */
+ {0x3808, 0x06},
+ {0x3809, 0x40},
+ {0x380a, 0x04},
+ {0x380b, 0xb0},
+
+ /* Set HTS + VTS to 1704x1294 */
+ {0x380c, 0x06},
+ {0x380d, 0xa8},
+ {0x380e, 0x05},
+ {0x380f, 0x0e},
+
+ /* Set ISP WIN X and Y start to 0x0 */
+ {0x3811, 0x00},
+ {0x3813, 0x00},
+
+ /* Set X INC and Y INC for non binning */
+ {0x3814, 0x11},
+ {0x3815, 0x11},
+
+ /* Initialize FORMAT1 to default/reset value (vflip disabled) */
+ {0x3820, 0xc0},
+
+ /* Set backlight compensation range start to 0 */
+ {0x4008, 0x00},
+
+ /* Set MIPI pclk period to default/reset value of 0x18 */
+ {0x4837, 0x18}
};
static const struct ov2680_mode_info ov2680_mode_init_data = {
--
2.41.0
