Re: [PATCH v14 18/18] media: i2c: ds90ub953: Support non-sync mode

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On 19/06/2023 13:48, Andy Shevchenko wrote:
On Mon, Jun 19, 2023 at 12:00:57PM +0300, Tomi Valkeinen wrote:
On 16/06/2023 17:47, Andy Shevchenko wrote:
On Fri, Jun 16, 2023 at 04:59:22PM +0300, Tomi Valkeinen wrote:
Add support for FPD-Link non-sync mode with external clock. The only
thing that needs to be added is the calculation for the clkout.

...

+	switch (priv->mode) {
+	case UB953_MODE_SYNC:
+		if (priv->hw_data->is_ub971)
+			return priv->plat_data->bc_rate * 160ull;
+		else
+			return priv->plat_data->bc_rate / 2 * 160ull;

Redundant 'else'.

True, but I like the symmetry in:

if (foo)
	return 123;
else
	return 321;

At the same time it will be symmetry with other switch-case(s). That's why the
question about fallthrough below.

Do I understand correctly you don't want to fallthrough because it will give
±160 in the rate (depending if it's even or odd)?

Sorry, can you clarify? Fallthrough to what?

To the below case since '/ 2 * 160 ~= *80'. Why ~ because it might give
off-by-one error due to even/odd input.

The below case is different. "priv->plat_data->bc_rate" vs "clk_get_rate(priv->clkin)".

As to the order of the calculation (/ 2 * 160 versus * 160 / 2), generally speaking, I have never figured out what are the correct ways to calculate clock rates.

I wrote "x / 2 * 160" as that's what the documentation gives (there's a hardware /2 divider in non-ub971 chips, followed by a 160 multiplier). But does the documentation presume that the calculation is done precisely, not in integers? If so, "x * 160 / 2" would be better (but then, do we need to round?). Or does the /2 hardware divider basically actually work as a an integer division, in case "x / 2 * 160" is the correct one.

+	case UB953_MODE_NONSYNC_EXT:
+		/* CLKIN_DIV = 1 always */
+		return clk_get_rate(priv->clkin) * 80ull;


 Tomi




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