The external clock frequency times the PLL multiplier may exceed the value
range of 32-bit unsigned integers. Instead perform the same calculation y
using two divisions.
The result has some potential to be different, but that's ok: this number
is used to limit the range of pre-PLL divisors to find optimal values. So
the effect of the rare case of a different result here would mean an
invalid pre-PLL divisor is tried. That will be found out a little later in
any case.
Also guard against dividing by zero if the external clock frequency is
higher than the maximum OP PLL output clock --- a rather improbable case.
Signed-off-by: Sakari Ailus <sakari.ailus@xxxxxxxxxxxxxxx>
---
drivers/media/i2c/ccs-pll.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index b45e6b30c528..78897a7c1448 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -40,6 +40,11 @@ static inline uint32_t is_one_or_even(uint32_t a)
return 1;
}
+static inline uint32_t one_or_more(uint32_t a)
+{
+ return a ?: 1;
+}
+
static int bounds_check(struct device *dev, uint32_t val,
uint32_t min, uint32_t max, char *str)
{
@@ -458,8 +463,10 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
min_op_pre_pll_clk_div =
max_t(uint16_t, min_op_pre_pll_clk_div,
clk_div_even_up(
- DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
- op_lim_fr->max_pll_op_clk_freq_hz)));
+ mul /
+ one_or_more(
+ DIV_ROUND_UP(op_lim_fr->max_pll_op_clk_freq_hz,
+ pll->ext_clk_freq_hz))));
dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n",
min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
--
2.27.0
