Add defalt value for the DVP interface synchronism signals. The default values have been derived from register 0x4740 documentation (datasheet version 2.03) 0x4740 POLARITY CTRL00 default = 0x20 bit 5: pclk polarity = 1 active high bit 1: HREF polarity = 0 active low bit 0: VSYNC polarity = 0 active low Signed-off-by: Jacopo Mondi <jacopo+renesas@xxxxxxxxxx> --- Documentation/devicetree/bindings/media/i2c/ov5640.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/media/i2c/ov5640.yaml b/Documentation/devicetree/bindings/media/i2c/ov5640.yaml index ab700a1830aa..3c20cdd02f76 100644 --- a/Documentation/devicetree/bindings/media/i2c/ov5640.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ov5640.yaml @@ -94,12 +94,15 @@ properties: hsync-active: enum: [0, 1] + default: 0 vsync-active: enum: [0, 1] + default: 0 pclk-sample: enum: [0, 1] + default: 1 allOf: - if: -- 2.27.0