Re: [PATCH 3/4] ARM: dts: rockchip: add rk3288 ISP and DPHY

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Sure thanks for the comments, I will work on them and resubmit the patches.

On Wed, Apr 1, 2020 at 4:59 PM Helen Koike <helen.koike@xxxxxxxxxxxxx> wrote:
>
> Hi Karthik,
>
> Thanks for the patchset.
>
> On 3/31/20 4:54 AM, karthik poduval wrote:
> > ISP and DPHY device entries missing so add them.
> > ported over from https://github.com/TinkerBoard/debian_kernel.git
>
> If you've ported the changes from https://github.com/TinkerBoard/debian_kernel.git, I wonder if this should have a different Author and Signed-off-by.
>
> Please check: https://patchwork.kernel.org/bundle/tfiga/rkisp1-v6/
>
> Also, we usually don't add links in the commit message, since this will stay in the history,
> and links can be volatile.
>
> But you can add comments after the 3 dashes below, and they will be ignored when
> the maintainers applies it.
>
> >
> > Reported-by: Karthik Poduval <karthik.poduval@xxxxxxxxx>
>
> The Reported-by tag doesn't make much sense to me here, please check
>
>     Documentation/process/submitting-patches.rst
>
>
> > Signed-off-by: Karthik Poduval <karthik.poduval@xxxxxxxxx>
> > ---
>
> Comments can be added here, after these 3 dashes.
>
>
> Please, take into consideration the above comments for the other patches in the series as well.
>
> Regards,
> Helen
>
> >  arch/arm/boot/dts/rk3288.dtsi | 25 +++++++++++++++++++++++++
> >  1 file changed, 25 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> > index 9beb662166aa..adea8189abd9 100644
> > --- a/arch/arm/boot/dts/rk3288.dtsi
> > +++ b/arch/arm/boot/dts/rk3288.dtsi
> > @@ -247,6 +247,23 @@
> >          ports = <&vopl_out>, <&vopb_out>;
> >      };
> >
> > +    isp: isp@ff910000 {
> > +        compatible = "rockchip,rk3288-rkisp1";
> > +        reg = <0x0 0xff910000 0x0 0x4000>;
> > +        interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> > +        clocks = <&cru SCLK_ISP>, <&cru ACLK_ISP>,
> > +             <&cru HCLK_ISP>, <&cru PCLK_ISP_IN>,
> > +             <&cru SCLK_ISP_JPE>;
> > +        clock-names = "clk_isp", "aclk_isp",
> > +                  "hclk_isp", "pclk_isp_in",
> > +                  "sclk_isp_jpe";
> > +        assigned-clocks = <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>;
> > +        assigned-clock-rates = <400000000>, <400000000>;
> > +        power-domains = <&power RK3288_PD_VIO>;
> > +        iommus = <&isp_mmu>;
> > +        status = "disabled";
> > +    };
> > +
> >      sdmmc: mmc@ff0c0000 {
> >          compatible = "rockchip,rk3288-dw-mshc";
> >          max-frequency = <150000000>;
> > @@ -891,6 +908,14 @@
> >              status = "disabled";
> >          };
> >
> > +        mipi_phy_rx0: mipi-phy-rx0 {
> > +            compatible = "rockchip,rk3288-mipi-dphy-rx0";
> > +            clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_CSI>;
> > +            clock-names = "dphy-ref", "pclk";
> > +            #phy-cells = <0>;
> > +            status = "disabled";
> > +        };
> > +
> >          io_domains: io-domains {
> >              compatible = "rockchip,rk3288-io-voltage-domain";
> >              status = "disabled";
> >



-- 
Regards,
Karthik Poduval



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